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FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a-port) product specification supersedes data of 1998 may 11 ic23 data handbook 1999 apr 27 integrated circuits
philips semiconductors product specification FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a-port) 2 1999 apr 27 853-2040 21374 features ? 7-bit btl transceiver ? separate i/o on ttl a-port ? inverting ? three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit arrangement ? drives heavily loaded backplanes with equivalent load impedances down to 10 w . ? high drive 100ma btl open collector drivers on b-port ? allows incident wave switching in heavily loaded backplane buses ? reduced btl voltage swing produces less noise and reduces power consumption ? built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity ? compatible with ieee futurebus+ or proprietary btl backplanes ? controlled output ramp and multiple gnd pins minimize ground bounce ? each btl driver has a dedicated bus gnd for a signal return ? glitch-free power up/power down operation ? low i cc current ? tight output skew ? supports live insertion ? pins for the optional jtag boundary scan function are provided ? high density packaging in plastic quad flatpack ? 5v compatible i/o on a-port ? industrial temperature range option available as FBL2041i description the FBL2041/FBL2041i is a 7-bit bidirectional btl transceiver and is intended to provide the electrical interface to a high performance wired-or bus. the FBL2041 is an inverting transceiver. the b-port drivers are low-capacitance open collectors with controlled ramp and are designed to sink 100ma. precision band gap references on the b-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55v. the FBL2041/FBL2041i is pin and function compatible with fb2041 but operates at a 3.3v supply voltage, greatly reducing power consumption. the b-port interfaces to abackplane transceiver logico (see the ieee 1194.1 btl standard). btl features low power consumption by reducing voltage swing (1vp-p, between 1v and 2v) and reduced capacitive loading by placing an internal series diode on the drivers. btl also provides incident wave switching, a necessity for high performance backplanes. there are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit arrangement. the ttl/btl output drivers for bit 0 are enabled with oea1/oeb1 , output drivers for bits 123 are enabled with oea2/oeb2 and output drivers for bits 456 are enabled with oea3/oeb3 . the a-port operates at ttl levels with separate i/o. the 3-state a-port drivers are enabled when oean goes high after an extra 6ns delay which is built in to provide a break-before-make function. when oean goes low, a-port drivers become high impedance without any extra delay. during power on/off cycles, the a-port drivers are held in a high impedance state when v cc is below 1.3v. the b-port has an output enable, oeb0, which affects all seven drivers. when oeb0 is high and oebn is low the output driver will be enabled. when oeb0 is low or if oebn is high, the b-port drivers will be inactive and at the level of the backplane signal. to support live insertion, oeb0 is held low during power on/off cycles to insure glitch free b port drivers. proper bias for b port drivers during live insertion is provided by the bias v pin when at a 3.3v level while v cc is low. if live insertion is not a requirement, the bias v pin should be tied to a v cc pin. the logic gnd and bus gnd pins are isolated in the package to minimize noise coupling between the btl and ttl sides. these pins should be tied to a common ground external to the package. each btl driver has an associated bus gnd pin that acts as a signal return path and these bus gnd pins are internally isolated from each other. in the event of a ground return fault, a ahardo signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble-shoot. jtag boundary scan functionality is provided as an option with signals tms, tck, tdi and tdo. when this option is not present, tms and tck are no-connects (no bond wires) and tdi and tdo are shorted together internally. quick reference data symbol parameter typical unit t plh propagation delay 4.2 ns t phl ain to bn 3.5 ns t plh propagation delay 4.8 ns t phl bn to aon 4.9 ns c ob output capacitance (b0 - b6 only) 6 pf i ol output current (b0 - b6 only) 100 ma standby 5.2 i cc su pp ly current ain to bn (outputs low or high) 3.2 ma i cc su ly current bn to aon (outputs low) 13.5 ma bn to aon (outputs high) 10.7 ordering information package commercial range v cc = 3.3v 10%; t amb = 0 to +70 c industrial range v cc = 3.3v 10%; t amb = 40 to +85 c dwg no. 52-pin plastic quad flatpack FBL2041 bb FBL2041i bb sot379-1
philips semiconductors product specification FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a-port) 1999 apr 27 3 pin configuration 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 bus gnd b1 bus gnd b2 bus gnd b3 bus gnd b4 bus gnd b5 bus gnd b6 n/c logic gnd ai1 ai2 ao2 logic gnd ao3 logic gnd ai3 ai4 ao4 logic gnd ao5 logic gnd ai5 logic gnd ao6 logic gnd tdo (option) tdi (option) ai6 oeb3 bus v cc logic v cc ao1 ao0 oea1 tck (option) tms (option) bus gnd oeb1 bias v b0 bus v cc logic v cc oeb0 7-bit transceiver 52-lead pqfp ai0 oeb2 oea3 oea2 sg00115 pin description symbol pin number type name and function ai0 ai6 51, 2, 3, 8, 9, 14, 18 input data inputs (ttl) ao0 ao6 50, 52, 4, 6, 10, 12, 16 output 3-state outputs (ttl) b0 b6 40, 38, 36, 34, 32, 30, 28 i/o data inputs/open collector outputs, high current drive (btl) oeb0 46 input enables the bn outputs when high oeb1 45 input enables the b0 output when low oeb2 25 input enables the b1 b3 outputs when low oeb3 26 input enables the b4 b6 outputs when low oea1 47 input enables the a0 outputs when high oea2 20 input enables the a1 a3 outputs when high oea3 24 input enables the a4 a6 outputs when high bus gnd 41, 39, 37, 35, 33, 31, 29 gnd bus ground (0v) logic gnd 1, 5, 7, 11, 13, 15, 19 gnd logic ground (0v) bus v cc 23, 43 power positive supply voltage logic v cc 17, 49 power positive supply voltage band gap bias v 48 power positive supply voltage tms 42 input test mode select (no-connect) tck 44 input test clock (no-connect) tdi 22 input test data in (shorted to tdo) tdo 21 output test data out (tdi) n/c 27 e not connected
philips semiconductors product specification FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a-port) 1999 apr 27 4 function table mode inputs outputs mode ain bn * oeb0 oeb1 oeb2 oeb3 oea1 oea2 oea3 aon bn * l e h l l l l l l z h** ain to bn h e h l l l l l l z l l e h l l l h h h l h** h e h l l l h h h h l l e h l x x l l l z h** ai0 to b0 h e h l x x l l l z l l e h l x x h h h l h** h e h l x x h h h h l l e h x l x l l l z h** ai1 ai3 to b1 b3 h e h x l x l l l z l l e h x l x h h h l h** h e h x l x h h h h l l e h x x l l l l z h** ai4 ai6 to b4 b6 h e h x x l l l l z l l e h x x l h h h l h** h e h x x l h h h h l disable bn outputs x x l x x x x x x x h** x x x h h h x x x x h** disable b0 outputs x x h h x x x x x x h** disable b1 b3 outputs x x h x h x x x x x h** disable b4 b6 outputs x x h x x h x x x x h** x l l x x x h h h h input bn to aon x h l x x x h h h l input x l x h h h h h h h input x h x h h h h h h l input x l l x x x h x x h input b0 to ao0 x h l x x x h x x l input x l x h h h h x x h input x h x h h h h x x l input x l l x x x x h x h input b1 b3 to ao1 ao3 x h l x x x x h x l input x l x h h h x h x h input x h x h h h x h x l input x l l x x x x x h h input b4 b6 to ao4 ao6 x h l x x x x x h l input x l x h h h x x h h input x h x h h h x x h l input disable aon outputs x x x x x x l l l z x disable ao0 outputs x x x x x x l x x z x disable ao1 ao3 outputs x x x x x x x l x z x disable ao4 ao6 outputs x x x x x x x x l z x notes: h = high voltage level l = low voltage level x = don't care z = high-impedance (off) state e = input not externally driven h** = goes to level of pull-up voltage b* = precaution should be taken to ensure b inputs do not float. if they do, they are equal to low state.
philips semiconductors product specification FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a-port) 1999 apr 27 5 logic diagram sg00116 46 45 oeb0 oeb1 47 oea1 btl levels ttl levels tms tck tdi tdo 42 44 22 21 (future jtag boundary scan option) logic v cc = 17, 49 logic gnd = 1, 5, 7, 11, 13, 15, 19 bus v cc = 23, 43 bus gnd = 29, 31, 33, 35, 37, 39, 41 bias v = 48 51 ai0 50 ao0 b0 40 25 oeb2 38 b1 20 2 52 oea2 ai1 ao1 36 3 4 b2 ai2 ao2 34 8 6 b3 ai3 ao3 26 32 24 9 10 30 14 12 28 18 16 oeb3 b4 oea3 ai4 ao4 b5 ai5 ao5 b6 ai6 ao6
philips semiconductors product specification FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a-port) 1999 apr 27 6 absolute maximum ratings operation beyond the limits set forth in this table may impair the useful life of the device. unless otherwise noted these limits are over the operating free-air temperature range. symbol parameter rating unit v cc supply voltage 0.5 to +4.6 v v in p ut voltage ai0 ai6, oeb0, oebn , oean 0.5 to +7.0 v in inp u t v oltage b0 b6 0.5 to +3.5 v i in input current v in 0 50 v out voltage applied to output in high output state 0.5 to +7.0 v i o current applied to output in ao0 ao6 64, 64 ma i out low output state/high output state b0 b6 200 ma t stg storage temperature 65 to +150 c recommended operating conditions symbol parameter commercial limits v cc = 3.3v 10%; t amb = 0 to +70 c industrial limits v cc = 3.3v 10%; t amb = 40 to +85 c unit min typ max min typ max v cc supply voltage 3.0 3.3 3.6 3.0 3.3 3.6 v v high level in p ut voltage except b0 b6 2.0 2.0 v v ih high - le v el inp u t v oltage b0 b6 1.62 1.55 1.62 1.55 v v low level in p ut voltage except b0 b6 0.8 0.8 v v il lo w- le v el inp u t v oltage b0 b6 1.47 1.47 v i ik input clamp current 18 18 ma i oh high-level output current ao0 ao6 32 32 ma i o low level out p ut current ao0 ao6 +32 +32 ma i ol lo w- le v el o u tp u t c u rrent b0 b6 100 100 ma c ob output capacitance on b port 6 7 6 7 pf t amb operating free-air temperature range 0 +70 40 +85 c live insertion specifications symbol parameter limits unit symbol parameter min typ max unit v biasv bias pin voltage voltage difference between the bias voltage and v cc after the pcb is plugged in. 0.5 v i s bias p in (i s )in p ut dc current v cc = 0 v, bias v = 3.6v 1.2 ma i biasv bias pin (i biasv ) inp u t dc c u rrent v cc = 3.3v, bias v = 3.6v 10 m a v bn bus voltage during prebias b0 b8 = 0v, bias v = 3.3v 1.62 2.1 v i lm fall current during prebias b0 b8 = 2v, bias v = 1.3 to 2.5v 1 m a i hm rise current during prebias b0 b8 = 1v, bias v = 3 to 3.6v 1 m a i bn peak peak bus current during insertion v cc = 0 to 3.3v, b0 b8 = 0 to 2.0v, bias v = 2.7 to 3.6v, oeb0 = 0.8v, t r = 2ns 10 ma i o off power u p current v cc = 0 to 3.3v, oeb0 = 0.8v 100 m a i ol off po w er u p c u rrent v cc = 0 to 1.2v, oeb0 = 0 to 5v 100 m a t gr input glitch rejection v cc = 3.3v 1.0 1.35 ns
philips semiconductors product specification FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a-port) 1999 apr 27 7 dc electrical characteristics over recommended operating free-air temperature range unless otherwise noted. symbol parameter test conditions 1 limits unit symbol parameter test conditions 1 min typ 2 max unit i oh high level output current b0 b6 v cc = max, v il = max, v oh = 1.9v 100 m a i o power off out p ut current b0 b6 v cc = 0v, v il = max, v oh = 1.9v 100 m a i off po w er - off o u tp u t c u rrent b0 b6 v cc = 0v, v il = max, v oh = 1.9v @ 85 c 300 m a hi h l l t t 3 v cc = min to max; i oh = -100 m a v cc 0.2 v v oh high-level output voltage ao0 ao6 3 v cc = min; i oh = -8ma 2.4 v voltage v cc = min; i oh = -32ma 2.0 v ao0 ao6 3 v cc = min; i ol = 16ma 0.4 v v ol low-level output voltage ao0 ao6 3 v cc = min; i ol = 32ma 0.5 v b0 b6 v cc = min, i ol = 4ma 0.5 v b0 b6 v cc = min, i ol = 100ma 0.75 1.0 1.20 v v ik input clamp voltage v cc = min, i i = i ik = 18ma 0.85 -1.2 v control pins v cc = 3.6v; v i = v cc or gnd 1.0 i in p ut leakage current control/ ai0 ai6 v cc = 0v or 3.6v; v i = 5.5v 10 m a i i inp u t leakage c u rrent ai0 ai6 v cc = 3.6v; v i = v cc 1 m a note 4 v cc = 3.6v; v i = 0v 5 v cc = max, v i = 1.9v 100 m a i ih high-level input current b0 b6 v cc = max, v i = 3.5v, note 5 100 ma v cc = max; v i = 3.75v @ 40 c 100 ma i il low-level input current b0 b6 v cc = max, v i = 0.75v -100 m a i ozh off-state output current ao0 ao6 v cc = max, v o =3v 5 m a i ozl off-state output current ao0 ao6 v cc = max, v o = 0.5v -5 m a i ccz v cc = max 5.2 13.5 i cc su pp ly current (total) i ccb v cc = max, outputs low or high 3.2 9.0 ma i cc s u ppl y c u rrent (total) i ccl v cc = max, outputs low 13.5 19.5 ma i cch v cc = max, outputs high 10.7 16.0 notes: 1. for conditions shown as min or max, use the appropriate value specified under recommended operation conditions for the applic able type. 2. all typical values are at v cc = 3.3v, t a = 25 c. 3. due to test equipment limitations, actual test conditions are v ih = 1.8v and v il = 1.3v for the b side. 4. unused pins are at v cc or gnd. 5. for b port input voltage between 3 and 5 volt; i ih will be greater than 100ma but the part will continue to function normally (clamping circuit is active).
philips semiconductors product specification FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a-port) 1999 apr 27 8 ac electrical characteristics a port limits test t amb = +25 c, FBL2041 commercial FBL2041i industrial symbol parameter test condition amb , v cc = 3.3v, c l = 50pf, r l = 500 w t amb = 0 to +70 c, v cc = 3.3v 10%, c l = 50pf, r l = 500 w t amb = 40 to +85 c, v cc = 3.3v 10%, c l = 50pf, r l = 500 w unit min typ max min max min max t plh t phl propagation delay, bn to aon waveform 1, 2 3.9 4.0 4.8 4.9 5.8 6.0 3.7 3.8 6.4 6.7 2.8 2.7 6.9 7.0 ns t pzh t pzl output enable time, oea to aon waveform 4, 5 5.3 2.4 6.6 4.4 8.0 8.0 5.0 2.1 8.6 8.5 4.5 1.1 9.0 9.0 ns t phz t plz output disable time, oea to aon waveform 4, 5 3.5 2.3 4.8 3.1 6.0 3.9 3.4 2.2 6.5 4.3 2.7 1.4 7.0 4.7 ns t tlh t thl transition time, aon port (10% to 90% or 90% to 10%) test circuit and waveforms 0.7 0.5 1.8 1.6 3.0 2.0 0.7 0.5 3.0 2.0 0.7 0.5 3.0 2.0 ns t sk (o) output skew between receivers in same package 1 waveform 3 0.7 1.5 1.5 1.5 ns b port limits symbol parameter test condition t amb = +25 c, v cc = 3.3v, c d = 30pf, r u = 9 w t amb = 0 to +70 c, v cc = 3.3v 10%, c d = 30pf, r u = 9 w t amb = 40 to +85 c, v cc = 3.3v 10%, c d = 30pf, r u = 9 w unit t plh t phl propagation delay, ain to bn waveform 1, 2 3.3 2.7 4.2 3.5 5.2 4.5 2.9 2.5 6.0 5.0 1.8 1.7 6.7 5.6 ns t plh t phl enable/disable time, oeb0 to bn waveform 2 4.0 3.4 4.9 4.3 5.8 5.3 3.6 3.1 6.6 6.0 2.8 2.5 7.1 6.4 ns t plh t phl enable/disable time, oeb1 to bn waveform 1 4.2 2.9 5.1 3.8 6.1 4.7 3.9 2.6 6.9 5.5 2.9 1.9 7.3 6.0 ns t tlh t thl transition time, bn port (1.3v to 1.8v) test circuit and waveforms 1.2 0.4 2.4 0.9 3.0 1.5 1.2 0.4 3.0 1.5 1.2 0.4 3.0 1.5 ns t sk (o) output skew between drivers in same package 1 waveform 3 1.5 1.5 1.5 ns symbol parameter test condition r u = 16.5 w r u = 16.5 w r u = 16.5 w unit t plh t phl propagation delay, ain to bn waveform 1, 2 3.3 2.7 4.2 3.6 5.1 4.5 3.0 2.5 6.0 5.0 1.8 1.7 6.7 5.6 ns t plh t phl enable/disable time, oeb0 to bn waveform 2 4.0 3.4 4.9 4.3 5.8 5.3 3.6 3.1 6.6 6.0 2.7 2.5 7.1 6.4 ns t plh t phl enable/disable time, oeb1 to bn waveform 1 4.2 2.9 5.1 3.8 6.1 4.7 3.9 2.6 6.8 5.5 3.0 1.9 7.3 6.0 ns t tlh t thl transition time, bn port (1.3v to 1.8v) test circuit and waveforms 1.2 0.4 2.4 0.9 3.0 1.5 1.2 0.4 3.0 1.5 1.2 0.4 3.0 1.5 ns t sk (o) output skew between drivers in same package 1 waveform 3 1.5 1.5 1.5 ns notes: 1. ? t pn actual t pm actual ? for any data input to output path compared to any other data input to output path where n and m are either lh or hl. skew times are valid only under same test conditions (temperature, v cc , loading, etc.).
philips semiconductors product specification FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a-port) 1999 apr 27 9 ac waveforms v m = 1.55v for bn , v m = 1.5v for all others. ain, bn or bn oebn aon or bn v m v m v m v m t plh t phl sg00101 waveform 1. propagation delay for data or output enable to output v m v m v m v m t phl t plh aon, bn ain, bn oeb0 sg00102 waveform 2. propagation delay for data or output enable to output ain, bn aon, bn v m v m t sk (o) sg00103 waveform 3. output skews aon oea v m v m v m v oh -0.3v ov t phz t pzh sg00104 waveform 4. 3-state output enable time to high level and output disable time from high level t pzl aon oea v m v m t plz v m v ol +0.3v sg00105 waveform 5. 3-state output enable time to low level and output disable time from low level
philips semiconductors product specification FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a-port) 1999 apr 27 10 test circuit and waveforms 2.5ns 2.5ns 500ns 500ns input pulse requirements rep. rate amplitude t tlh t thl 1mhz 3.0v 2.5ns input pulse definitions v m = 1.55v for bn , v m = 1.5v for all others. v cc family fb+ d.u.t. pulse generator 6.0v r l r l c l r t v in v out test circuit for 3-state outputs on a port test switch switch position for all a-ports t plh, t phl open definitions: r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. c d = load capacitance includes jig and probe capacitance; see ac characteristics for value. r u = pull up resistor; see ac characteristics for value. t w 90% v m 10% 90% v m 10% 90% v m 10% 90% v m 10% negative pulse positive pulse low v low v t thl (t f ) t tlh (t r ) t w bias v t w low v 0.0v t tlh (t r ) t thl (t f ) a port 1mhz 2.0v 2.5ns 1.0v b port v cc d.u.t. pulse generator r u c d r t v in v out test circuit for outputs on b port bias v 2.0v (for r u = 9 w ) 2.1v (for r u = 16.5 w ) v in v in sg00090 t plz, t pzl closed t phz, t pzh gnd
philips semiconductors product specification FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a port) 1999 apr 27 11 qfp52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm sot379-1
philips semiconductors product specification FBL2041 FBL2041i 3.3v btl 7-bit futurebus+ transceiver (standard a port) 1999 apr 27 12 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1999 all rights reserved. printed in u.s.a. date of release: 11-99 document order number: 9397 750 06597

data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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